Vipin Kizheppatt

Generating custom AXI4-Stream IP core using Xilinx Vivado

Generating custom AXI4-Stream IP core using Xilinx Vivado Vipin Kizheppatt 11K 36,733 4 года назад

Hardware Software CoDesign with Vivado and Vitis

Hardware Software CoDesign with Vivado and Vitis Vipin Kizheppatt 4K 13,234 3 года назад

Neural Networks on FPGA: Part 1: Introduction

Neural Networks on FPGA: Part 1: Introduction Vipin Kizheppatt 23K 75,489 4 года назад

Developing an SPI Controller for Zedboard OLED Display

Developing an SPI Controller for Zedboard OLED Display Vipin Kizheppatt 6K 19,221 4 года назад

An Introduction to FPGAs: Architecture, Programmability and Advantageous

An Introduction to FPGAs: Architecture, Programmability and Advantageous Vipin Kizheppatt 14K 45,351 5 лет назад

AM Modulator Part-1

AM Modulator Part-1 Vipin Kizheppatt 189 630 3 месяца назад

Image Processing on Zynq (FPGAs) : Part 1 Introduction

Image Processing on Zynq (FPGAs) : Part 1 Introduction Vipin Kizheppatt 16K 53,752 4 года назад

Developing application software for Xilinx AXI DMA

Developing application software for Xilinx AXI DMA Vipin Kizheppatt 10K 33,076 4 года назад

ZyMouse: Developing a mouse for Zedboard

ZyMouse: Developing a mouse for Zedboard Vipin Kizheppatt 248 828 4 года назад

Ethernet with Standalone

Ethernet with Standalone Vipin Kizheppatt 227 758 3 месяца назад

Histogram Equalization IP

Histogram Equalization IP Vipin Kizheppatt 225 750 3 месяца назад

Drivers for custom IP

Drivers for custom IP Vipin Kizheppatt 3K 9,387 4 года назад

Partial Reconfiguration: Part 1 Introduction

Partial Reconfiguration: Part 1 Introduction Vipin Kizheppatt 2K 6,172 4 года назад

Vivado for FPGA design: Part 1 Installation and licensing

Vivado for FPGA design: Part 1 Installation and licensing Vipin Kizheppatt 4K 13,004 4 года назад

Partial Reconfiguration: Part 4 Processor Configuration Access Port (PCAP)

Partial Reconfiguration: Part 4 Processor Configuration Access Port (PCAP) Vipin Kizheppatt 837 2,790 4 года назад

Connect6 on Zynq (FPGA): Part 1 Introduction

Connect6 on Zynq (FPGA): Part 1 Introduction Vipin Kizheppatt 329 1,096 4 года назад

Xilinx XSCT Part 1: Transferring Image data between Computer and Zedboard

Xilinx XSCT Part 1: Transferring Image data between Computer and Zedboard Vipin Kizheppatt 3K 9,102 4 года назад

In-System Debugging with Vivado Using ILA Core

In-System Debugging with Vivado Using ILA Core Vipin Kizheppatt 12K 41,400 4 года назад

Designing a custom IP for Merge Operation with Xilinx Fifo Generator

Designing a custom IP for Merge Operation with Xilinx Fifo Generator Vipin Kizheppatt 2K 7,609 4 года назад

Image Processing on Zynq (FPGAs) : Part 2 Design of Line buffer

Image Processing on Zynq (FPGAs) : Part 2 Design of Line buffer Vipin Kizheppatt 10K 34,804 4 года назад

Vipin Kizheppatt. Смотреть видео: Generating Custom AXI4 Stream IP Core Using Xilinx Vivado, Hardware Software CoDesign With Vivado And Vitis, Neural Networks On FPGA Part 1 Introduction, Developing An SPI Controller For Zedboard OLED Display.